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data sheet idt8v41n004nlgi revision a december 18 , 2012 1 ?2012 integrated device technology, inc. femtoclock ? ng crystal-to-hcsl clock generator IDT8V41N004I general description the IDT8V41N004I is a clock generator designed for gigabit ethernet, 10 gigabit ethernet, sgmii and pci express? applications. the device generates a selectable 100mhz, 125mhz, 156.25mhz or 312.5mhz clock signal from 25mhz input. the IDT8V41N004I uses idt?s fourth generation femtoclock ? ng technology to provide low phase noise performance, combined with excellent power supply noise rejection for optimal performance in the targeted applications. the device su pports a 3.3v supply voltage and is packaged in a compact, lead-free (rohs 6) 32-lead vfqfn package. the industrial temperature range supports high end computing, telecommunication and networking end equipment requirements. features ? fourth generation femtoclock ? ng technology ? four 100mhz, 125mhz, 156.25mhz and 312.5mhz clocks for gigabit ethernet, 10 gigabit et hernet, sgmii and pci express applications, hcsl interface levels ? selectable external crystal or differential input source ? crystal oscillator interface designed for 25mhz parallel resonant crystal ? differential clk, nclk input pair accepts lvpecl, lvds, lvhstl, hcsl input levels ? internal resistor bias on nclk pin allows the user to drive clk input with external single-ended (lvcmos/ lvttl) input levels ? pci express gen1, gen2, and gen 3 compliant ? rms phase jitter 156.25mhz (12khz - 20mhz): 0.217ps ? full 3.3v supply voltage ? -40c to 85c ambient operating temperature pin assignment 32 lead vfqfn 5mm x 5mm x 0.925mm package body 3.15mm x 3.15mm epad size nl package top view fsel1 fsel0 v dd xtal_out xtal_in clk_sel nref_out ref_out 16 15 14 13 12 11 10 9 24 23 22 21 20 19 18 17 q1 nq1 v dd q2 nq2 gnd q3 nq3 25 26 27 28 29 30 31 32 gnd nq0 q0 v dd oe3 oe2 v dd v dda pll_bypass oe_ref oe1 oe0 iref v dd clk nck IDT8V41N004I 12345678
idt8v41n004nlgi revision a december 18 , 2012 2 ?2012 integrated device technology, inc. IDT8V41N004I data sheet femtoclock ? ng crystal-to-hcsl clock generator block diagram pu/pd pulldown clk_sel xtal_in xtal_out clk nclk osc femtoclock ? ng pll 2.5ghz pulldown fsel[1:0] 00 16 01 25 10 20 11 8 pulldown pulldown pulldown pulldown pulldown pulldown oe0 oe1 oe2 oe3 oe_ref pulldown pulldown ref_out nref_out q0 nq0 q1 nq1 q2 nq2 q3 nq3 fsel1 fsel0 pll_bypass 0 1 1 0 iref x2
idt8v41n004nlgi revision a december 18 , 2012 3 ?2012 integrated device technology, inc. IDT8V41N004I data sheet femtoclock ? ng crystal-to-hcsl clock generator pin description and pin characteristic tables table 1. pin descriptions note: pullup and pulldown refer to internal input resistors. see table 2, pin characteristics, for typical values. number name type description 1 pll_bypass input pulldown active high pll bypass. lvcmos/lvttl interface levels. pll_bypass = 0: pll mode (default) pll_bypass = 1: bypass mode 2 oe_ref input pulldown active high output enable for ref_ out, nref_out differential output. lvcmos/lvttl interface levels. oe_ref = 0: output ref_out di sabled/high impedance (default) oe_ref = 1: output ref_out enabled 3oe1inputpulldown active high output enable for q1, nq 1 differential output. lvcmos/lvttl interface levels. oe1 = 0: output q1 disa bled/high impedance (default) oe1 = 1: output q1 enabled 4oe0inputpulldown active high output enable for q0, nq 0 differential output. lvcmos/lvttl interface levels. oe0 = 0: output q0 disa bled/high impedance (default) oe0 = 1: output q0 enabled 5 iref input external fixed precision resistor (475 ? ) from this pin to ground provides a reference current used for hcsl outputs. 6, 14, 22, 28, 31 v dd power supply voltage pins. 7 clk input pulldown non-inverting differential clock input. 8 nclk input pullup/ pulldown inverting differential clock input. v dd /2 default when left floating. 9, 10 ref_out, nref_out output differential reference clock ou tput pair. hcsl interface levels. 11 clk_sel input pulldown active high clock select input. sele cts pll input source. lvcmos /lvttl interface levels. clk_sel = 0: xtal_in, xtal_out (default) clk_sel = 1: clk, nclk 12, 13 xtal_in, xtal_out input crystal oscillator interface. xtal_i n is the input., xtal_out is the output. 15, 16 fsel0, fsel1 input pulldown output frequency select pins. lvcmos/lvttl interface levels. fsel[1:0] = 00: f out = 156.25mhz (default) fsel[1:0] = 01: f out = 100mhz fsel[1:0] = 10: f out = 125mhz fsel[1:0] = 11: f out = 312.5mhz 17, 18 nq3, q3 output differential outp ut pair. hcsl interface levels. 19, 25 gnd power power supply ground. 20, 21 nq2, q2 output differential outp ut pair. hcsl interface levels. 23, 24 nq1, q1 output differential outp ut pair. hscl interface levels. 26, 27 nq0, q0 output differential outp ut pair. hcsl interface levels. 29 oe3 input pulldown active high output enable fo r q3, nq3 differential output. lvcmos/lvttl interface levels. oe3 = 0: output q3 disa bled/high impedance (default) oe3 = 1: output q3 enabled 30 oe2 input pulldown active high output enable fo r q2, nq2 differential output. lvcmos/lvttl interface levels. oe2 = 0: output q2 disa bled/high impedance (default) oe2 = 1: output q2 enabled 32 v dda power analog supply voltage.
idt8v41n004nlgi revision a december 18 , 2012 4 ?2012 integrated device technology, inc. IDT8V41N004I data sheet femtoclock ? ng crystal-to-hcsl clock generator table 2. pin characteristics absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only . functional operation of product at t hese conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. dc electrical characteristics table 3a. power supply dc characteristics, v dd = 3.3v 5%, t a =-40c to 85c note 1: this device requires that v dd and v dda are powered simultaneously. see power supply sequence requirement application note. symbol parameter test conditio ns minimum typical maximum units c in input capacitance 3.5 pf r pullup input pullup resistor 51 k ? r pulldown input pulldown resistor 51 k ? item rating supply voltage, v dd 3.6v inputs, v i xtal_in other inputs 0v to 2v -0.5v to v dd + 0.5v outputs, v o -0.5v to v dd + 0.5v package thermal impedance, ? ja 33.1c/w (0 mps) storage temperature, t stg -65 ? c to 150 ? c symbol parameter test conditions minimum typical maximum units v dd core supply voltage 3.135 3.3 3.465 v v dda ; note 1 analog supply voltage v dd ? 0.155 3.3 v dd v i dd power supply current outputs disabled 121 ma i dda analog supply current 31 ma
idt8v41n004nlgi revision a december 18 , 2012 5 ?2012 integrated device technology, inc. IDT8V41N004I data sheet femtoclock ? ng crystal-to-hcsl clock generator table 3b. lvcmos/lvttl dc characteristics, v dd = 3.3v 5%, t a =-40c to 85c table 3c. differential dc characteristics, v dd = 3.3v 5%, t a =-40c to 85c note 1: common mode voltage is defined as the crosspoint. table 4. crystal characteristics note: characterized using a 12pf parallel resonant crystal. table 5. input frequency characteristics, v dd = 3.3v 5%, t a =-40c to 85c symbol parameter test conditio ns minimum typical maximum units v ih input high voltage 2 v dd + 0.3 v v il input low voltage -0.3 0.8 v i ih input high current fsel[1:0], clk_sel, oe_ref, pll_bypass, oe0, oe1, oe2, oe3 v dd = v in = 3.465v 150 a i il input low current fsel[1:0], clk_sel, oe_ref, pll_bypass, oe0, oe1, oe2, oe3 v dd = 3.465v, v in = 0v -5 a symbol parameter test conditio ns minimum typical maximum units i ih input high current clk, nclk v dd = v in = 3.465v 150 a i il input low current clk v dd = 3.465v, v in = 0v -5 a nclk v dd = 3.465v, v in = 0v -150 a v pp peak-to-peak input voltage 0.15 1.3 v v cmr common mode input voltage; note 1 gnd + 0.5 v dd ? 0.85 v parameter test conditions mi nimum typical maximum units mode of oscillation fundamental frequency 25 mhz load capacitance (c l ) 12 pf equivalent series resistance (esr) 50 ? shunt capacitance 7pf symbol parameter test conditio ns minimum typical maximum units f in input frequency xtal_in, xtal_out 25 mhz clk, nclk 25 mhz f in_dc input duty cycle clk, nclk 45 55 %
idt8v41n004nlgi revision a december 18 , 2012 6 ?2012 integrated device technology, inc. IDT8V41N004I data sheet femtoclock ? ng crystal-to-hcsl clock generator ac electrical characteristics table 6a. pci express jitter specifications, v dd = 3.3v 5%, t a = -40c to 85c note: electrical parameters are guaranteed over the specified am bient operating temperature rang e, which is established when th e device is mounted in a test socket with maintained transverse airflow greate r than 500 lfpm. the device will meet specifications after th ermal equilibrium has been reached under these conditions. fo r additional information, refer to the pci express applicat ion note section in the datasheet. note 1: peak-to-peak jitter after applying system transfer func tion for the common clock architecture. maximum limit for pci ex press gen 1 is 86ps peak-to-peak for a sample size of 10 6 clock periods. note 2: rms jitter after applying the two evaluation bands to the two transfer functions defined in the common clock architectu re and reporting the worst case results for each evaluation band. ma ximum limit for pci express generation 2 is 3.1ps rms for t refclk_hf_rms (high band) and 3.0ps rms for t refclk_lf_rms (low band). note 3: rms jitter after applying system transfer function for the common clock architecture. this specification is based on th e pci express base specification revi sion 0.7, october 2009 and is subject to change pending the final release version of the specification. note 4: this parameter is guaranteed by characterization. not tested in production. symbol parameter test condit ions minimum typical maximum pcie industry specification units t j (pcie gen 1) phase jitter peak-to-peak; note 1, 4 ? = 100mhz, 25mhz crystal input evaluation band: 0hz - nyquist (clock frequency/2) 11 18 86 ps t refclk_hf_rms (pcie gen 2) phase jitter rms; note 2, 4 ? = 100mhz, 25mhz crystal input high band: 1.5mhz - nyquist (clock frequency/2) 1.0 1.6 3.10 ps t refclk_lf_rms (pcie gen 2) phase jitter rms; note 2, 4 ? = 100mhz, 25mhz crystal input low band: 10khz - 1.5mhz 0.24 1.1 3.0 ps t refclk_rms (pcie gen 3) phase jitter rms; note 3, 4 ? = 100mhz, 25mhz crystal input evaluation band: 0hz - nyquist (clock frequency/2) 0.24 0.41 0.8 ps
idt8v41n004nlgi revision a december 18 , 2012 7 ?2012 integrated device technology, inc. IDT8V41N004I data sheet femtoclock ? ng crystal-to-hcsl clock generator table 6b. ac characteristics, v dd = 3.3v 5%, t a =-40c to 85c symbol parameter test conditions minimum typical maximum units f out output frequency q[0:3], nq[0:3] fsel [1:0] = 00 156.25 mhz q[0:3], nq[0:3] fsel[1:0] = 01 100 mhz q[0:3], nq[0:3] fsel[1:0] = 10 125 mhz q[0:3], nq[0:3] fsel[1:0] = 11 312.5 mhz ref_out xtal, clk, nclk = 25mhz 25 mhz ? n (100) single-side band noise power, 100hz from carrier 25mhz crystal input, f out = 156.25mhz -85 dbc/hz ? n (1k) single-side band noise power, 1khz from carrier 25mhz crystal input, f out = 156.25mhz -118 dbc/hz ? n (10k) single-side band noise power, 10khz from carrier 25mhz crystal input, f out = 156.25mhz -133 dbc/hz ? n (100k) single-side band noise power, 100khz from carrier 25mhz crystal input, f out = 156.25mhz -138 dbc/hz ? n (1m) single-side band noise power, 1mhz from carrier 25mhz crystal input, f out = 156.25mhz -143 dbc/hz ? n (10m) single-side band noise power, 10mhz from carrier 25mhz crystal input, f out = 156.25mhz -156 dbc/hz tjit(?) rms phase jitter (random); note 1, 2 100mhz, integration range (12khz to 20mhz) 0.219 ps 125mhz, integration range: 12khz ? 20mhz 0.205 ps 156.25mhz, integration range: 12khz ? 20mhz 0.217 ps 312.5mhz, integration range: 12khz ? 20mhz 0.215 ps t ref_out_rms phase jitter rms; note 1 25mhz crystal input integration range: 12khz - 5mhz 0.268 ps tsk(o) output skew; note 3, 4 q[0:3], nq[0:3] 100 ps t jit(cc) cycle-to-cycle jitter; note 3 pll mode 12 ps t jit(per) period jitter, rms; note 3 pll mode 3.8 ps t l pll lock time 30 ms v max absolute max. output voltage; note 5, 6 1150 mv v min absolute min. output voltage; note 5, 7 -300 mv v rb ringback voltage; note 8, 9 -100 100 mv t stable time before v rb is allowed; note 8, 9 500 ps
idt8v41n004nlgi revision a december 18 , 2012 8 ?2012 integrated device technology, inc. IDT8V41N004I data sheet femtoclock ? ng crystal-to-hcsl clock generator note: electrical parameters are guaranteed over the specified am bient operating temperature rang e, which is established when th e device is mounted in a test socket with maintained transverse airflow greate r than 500 lfpm. the device will meet specifications after th ermal equilibrium has been reached under these conditions. note 1: refer to phase noise plot section. note 2: ref_out, nref_out is disabled. note 3: this parameter is defined in accordance with jedec standard 65. note 4: defined as skew between outputs at the same supply volt age and with equal load conditions. measured at the output diffe rential cross points. note 5. measurement taken from a single ended waveform. note 6. defined as the maximum instantaneous voltage includi ng overshoot. see parameter measurement information section. note 7: defined as the minimum instantaneous voltage includ ing undershoot. see parameter measurement information section. note 8: measurement taken from a differential waveform. note 9: t stable is the time the differential clock must maintain a minimum 150mv differential voltage after rising/falling edges before it is allowed to drop back into the v rb 100 mv differential range. note 10: measured at crossing point where the instantaneous voltage value of the risi ng edge of qx+ equals the falling edge of qx-. note 11: refers to the total variation from the lowest crossi ng point to the highest, regardless of which edge is crossing. ref ers to all crossing points for this measurement. note 12:defined as the total variation of all crossing voltages of rising qx+ and falling qx-, this is the maximum allowed vari ance in vcross for any particular system. see paramete r measurement information section. note 13: measured from -150mv to +150mv on the differential wa veform (derived from q minus nq). the signal must be monotonic th rough the measurement region for rise and fall time. the 300mv meas urement window is centered on the differential zero crossing. v cross absolute crossing voltage; note 5, 10, 11 f out = 100mhz 230 550 mv ? v cross total variation of v cross over all edges; note 5, 10, 12 140 mv psnr power supply noise rejection 45 db t slew+ rising edge rate; note 8, 13 0.6 4.0 v/ns t slew- falling edge rate; note 8, 13 0.6 4.0 v/ns odc output duty cycle; note 8 q[0:3], nq[0:3] 25mhz crystal input 45 55 % symbol parameter test conditions minimum typical maximum units
idt8v41n004nlgi revision a december 18 , 2012 9 ?2012 integrated device technology, inc. IDT8V41N004I data sheet femtoclock ? ng crystal-to-hcsl clock generator typical phase noise at 156.25mhz offset frequency (hz) noise power (dbc/hz)
idt8v41n004nlgi revision a december 18 , 2012 10 ?2012 integrated device technology, inc. IDT8V41N004I data sheet femtoclock ? ng crystal-to-hcsl clock generator typical phase noise at 25m hz (ref_out, nref_out) offset frequency (hz) noise power (dbc/hz)
idt8v41n004nlgi revision a december 18 , 2012 11 ?2012 integrated device technology, inc. IDT8V41N004I data sheet femtoclock ? ng crystal-to-hcsl clock generator parameter measureme nt information 3.3v hcsl output load test circuit 1 differential input level period jitter 3.3v hcsl output load test circuit 2 cycle-to-cycle jitter output skew measurement point measurement point gnd 2pf 2pf 0v iref 0v v dda v dd 3.3v5% 3.3v5% this load condition is used for v max , v min, v rb, t stable, v cross, ? v cross and t slew measurements. v cmr cross points v pp nclk clk v dd gnd v oh v ref v ol mean period (first edge after trigger) reference point (trigger edge) 1 contains 68.26% of all measurements 2 contains 95.4% of all measurements 3 contains 99.73% of all measurements 4 contains 99.99366% of all measurements 6 contains (100-1.973x10 -7 )% of all measurements histogram 475 ? 50 ? 50 ? gnd 0v scope iref 0v this load condition is used for tjit(cc), tjit(per), tjit(?), t ref_out_rms , ? n , tsk(o), and odc measurements. 3.3v5% v dd v dda 3.3v5% ? ? ? ? t cycle n t cycle n+1 t jit(cc) = | t cycle n ? t cycle n+1 | 1000 cycles nq[0:3] q[0:3] t sk(o) nqx qy nqy qx
idt8v41n004nlgi revision a december 18 , 2012 12 ?2012 integrated device technology, inc. IDT8V41N004I data sheet femtoclock ? ng crystal-to-hcsl clock generator parameter measurement in formation, continued rms phase jitter differential measurement points for duty cycle/period single-ended measurement points for absolute cross point and swing differential measurement points for rise/fall edge rate pll lock time differential measurement points for ringback single-ended measurement points for delta cross point offset frequency f 1 f 2 phase noise plot area under curve defined by the offset frequency markers rms phase jitter = noise power 2 * * ? 1 * clock period (differential) positive duty cycle (differential) negative duty cycle (differential) q - nq 0.0v v cross_max v cross_min v max v min nq q q - nq -150mv +150mv 0.0v fall edge rate rise edge rate t st able t stable v rb v rb q - nq -150mv v rb = -100mv v rb = +100mv +150mv 0.0v ? v cross nq q
idt8v41n004nlgi revision a december 18 , 2012 13 ?2012 integrated device technology, inc. IDT8V41N004I data sheet femtoclock ? ng crystal-to-hcsl clock generator applications information recommendations for unused input and output pins inputs: clk/nclk inputs for applications not requiring the us e of the differential input, both clk and nclk can be left floating. though not required, but for additional protection, a 1k ? resistor can be tied from clk to ground. crystal inputs for applications not requiring the use of the crystal oscillator input, both xtal_in and xtal_out can be left floating. though not required, but for additional protection, a 1k ? resistor can be tied from xtal_in to ground. lvcmos control pins all control pins have internal pulldowns; additional resistance is not required but can be added for additional protection. a 1k ? resistor can be used. outputs: differential outputs all unused differential outputs c an be left floating. we recommend that there is no trace attached. both sides of the differential output pair should either be left floating or terminated. wiring the differential input to accept single-ended levels figure 1 shows how a differential input can be wired to accept single ended levels. the reference voltage v 1 = v dd /2 is generated by the bias resistors r1 and r2. the bypass capacitor (c1) is used to help filter noise on the dc bias. this bias circuit should be located as close to the input pin as possible. the ratio of r1 and r2 might need to be adjusted to position the v 1 in the center of the input voltage swing. for example, if the input clock swing is 2.5v and v dd = 3.3v, r1 and r2 value should be adjusted to set v 1 at 1.25v. the values below are for when both the single ended swing and v dd are at the same voltage. this configuration requi res that the sum of the output impedance of the driver (ro) and the series resistance (rs) equals the transmission line impedance. in addition, matched termination at the input will attenuate the signal in half. this can be done in one of two ways. first, r3 and r4 in parallel should equal the transmission line impedance. for most 50 ? applications, r3 and r4 can be 100 ? . the values of the resistors can be increased to reduce the loading for slower and weaker lvcmos driver. when using single-ended signaling, the noise rejection bene fits of differential signaling are reduced. even though the differential input can handle full rail lvcmos signaling, it is recommended that the amplitude be reduced. the datasheet specifies a lower differential amplitude, however this only applies to differential signals. for single-ended applications, the swing can be larger, however v il cannot be less than -0.3v and v ih cannot be more than v dd + 0.3v. though some of the recommended components might not be used, the pads should be placed in the layout. they can be utilized for debugging purposes. the datasheet specifications are characterized and guaranteed by using a differential signal. figure 1. recommended schematic for wiring a diff erential input to accept single-ended levels
idt8v41n004nlgi revision a december 18 , 2012 14 ?2012 integrated device technology, inc. IDT8V41N004I data sheet femtoclock ? ng crystal-to-hcsl clock generator differential clock input interface the clk /nclk accepts lvds, l vpecl, lvhstl, hcsl and other differential signals. both signals must meet the v pp and v cmr input requirements. figures 2a to 2e show interface examples for the clk/nclk input driven by the most common driver types. the input interfaces suggested here are exam ples only. please consult with the vendor of the driver component to confirm the driver termination requirements. for example, in figure 2a, the input termination applies for idt open emitter lvhstl drivers. if you are using an lvhstl driver from another vendor, use their termination recommendation. figure 2a. clk/nclk input driven by an idt open emitter lvhstl driver figure 2c. clk/nclk input driven by a 3.3v lvpecl driver figure 2e. clk/nclk input driven by a 3.3v hcsl driver figure 2b. clk/nclk input driven by a 3.3v lvpecl driver figure 2d. clk/nclk input driven by a 3.3v lvds driver r1 50 r2 50 1.8v zo = 50 zo = 50 clk nclk 3.3v lvhstl idt lvhstl driver differential input r3 125 r4 125 r1 84 r2 84 3.3v zo = 50 zo = 50 clk nclk 3.3v 3.3v lvpecl differential input hcsl *r3 33 *r4 33 clk nclk 3.3v 3.3v zo = 50 zo = 50 differential input r1 50 r2 50 *optional ? r3 and r4 can be 0 clk nclk differential input lvpecl 3.3v zo = 50 zo = 50 3.3v r1 50 r2 50 r2 50 3.3v r1 100 lvds clk nclk 3.3v receiver zo = 50 zo = 50
idt8v41n004nlgi revision a december 18 , 2012 15 ?2012 integrated device technology, inc. IDT8V41N004I data sheet femtoclock ? ng crystal-to-hcsl clock generator power supply sequence requirement the IDT8V41N004I has a power supply sequence requirement. this device requires that v dd and v dda are powered simultaneously. this device has been characterized using the recommended power supply filtering techniques in figure 4 . overdriving the xtal interface the xtal_in input can be overdriven by an lvcmos driver or by one side of a differential driver through an ac coupling capacitor. the xtal_out pin can be left floating. the amplitude of the input signal should be between 500mv and 1.8v and the slew rate should not be less than 0.2v/ns. for 3.3v lvcmos inputs, the amplitude must be reduced from full swing to at least half the swing in order to prevent signal interference with the power rail and to reduce internal noise. figure 3a shows an example of the interface diagram for a high speed 3.3v lvcmos driver. this c onfiguration requires that the sum of the output impedance of the driver (ro) and the series resistance (rs) equals the transmission line impedance. in addition, matched termination at the crystal input will attenuate the signal in half. this can be done in one of two ways. first, r1 and r2 in parallel should equal the transmission line impedance. for most 50 ? applications, r1 and r2 can be 100 ? . this can also be accomplished by removing r1 and changing r2 to 50 ? . the values of the resistors can be increased to reduce the loading for a slower and weaker lvcmos driver. figure 3b shows an example of the interface diagram for an lvpecl driver. this is a standard lvpecl termination with one side of the driver feeding the xtal_in input. it is recommended that all components in the schematics be placed in the layout. though some components might not be used, they can be utilized for debugging purposes. the datasheet specifications are characterized and guaranteed by using a quartz crystal as the input. figure 3a. general diagram for lvcmos driver to xtal input interface figure 3b. general diagram for lvpec l driver to xtal input interface vcc xtal_out xtal_in r1 100 r2 100 zo = 50 ohms rs ro zo = ro + rs c1 .1uf lvcmos driver xta l _ o u t xta l _ i n zo = 50 ohms c2 .1uf lvpecl driver zo = 50 ohms r1 50 r2 50 r3 50
idt8v41n004nlgi revision a december 18 , 2012 16 ?2012 integrated device technology, inc. IDT8V41N004I data sheet femtoclock ? ng crystal-to-hcsl clock generator schematic example figure 4 (next page) shows an example of an IDT8V41N004I application schematic. the schematic example focuses on functional connections and is intended as an example only. it may not represent the exact user configuration. refer to the pin description and functional tables in the datasheet to ensure that the logic control inputs are properly set. for example, oe[3:0] and fsel[1:0] can be configured from an fpga instead of set with pull up and pull down resistors as shown. for this device, the crystal load capacitors are required for proper operation. a 12pf parallel resonant 25mhz crystal is used. the load capacitance c1 = c2 = 1pf is recommended for frequency accuracy. depending on the parasitic of the pr inted circuit board layout, these values might require a slight adjustment to optimize the frequency accuracy. crystals with ot her load capacitance s pecifications can be used, but this will require adjusting c1 and c2. the schematic example shows two different hcsl output terminations; the standard termination when the hcsl receiver is on the same pcb as the IDT8V41N004I as well as the termination for a pcie add-in card. as with any high speed analog circuitry, the power supply pins are vulnerable to noise. to achieve optimum jitter performance, power supply isolation is required. the IDT8V41N004I provides separate power supply pins to isolate noise from coupling into the internal pll. in order to achieve the best possible filtering, it is highly recommended that the 0.1uf capacitors at the output of the lc filter be placed on the IDT8V41N004I side of the pcb as close to the corresponding power pin as possible. this is represented by the placement of these capacitors in the schematic. do not share ground vias; use at least one ground via per 0.1uf cap or crystal load cap. if space is limited, the ferrite beads, 10uf capacitors and the 0.1uf capacitors connected directly to 3.3v can be placed on the opposite side of the pcb. if space permits, place all filter components on the de vice side of the board. power supply filter recommendations are a general guideline to be used for reducing external noise from coupling into the devices. the filter performance is designed for a wide range of noise frequencies. this low-pass filter starts to a ttenuate noise at approximately 10khz. if a specific frequency noise compone nt is known, such as switching power supplies frequencies, it is recommended that component values be adjusted and if required, additional filtering be added. additionally, good general design practices for power plane voltage stability suggests adding bulk c apacitance in the local area of all devices.
idt8v41n004nlgi revision a december 18 , 2012 17 ?2012 integrated device technology, inc. IDT8V41N004I data sheet femtoclock ? ng crystal-to-hcsl clock generator figure 4. IDT8V41N004I schematic layout u1 pll_bypass 1 oe _re f 2 oe 1 3 oe 0 4 iref 5 clk 7 nclk 8 clk_sel 11 xta l _in 12 f sel 0 15 f sel 1 16 oe 3 29 oe 2 30 ref_out 9 nr ef_ ou t 10 xta l _out 13 nq3 17 q3 18 nq2 20 q2 21 nq1 23 q1 24 nq0 26 q0 27 vdd 6 vdd 14 vdd 22 vd d 28 vdd 31 vdda 32 gnd 19 gnd 25 epad 33 vdd vdd to logic input pins ru2 not inst all ru1 1k rd2 1k to log ic inp ut pin s rd1 n ot install l ogic control input e xamples set log ic input to '1' s et logic inpu t to '0' vdd nr ef _ ou t q0 q2 q1 nq 1 nq 0 q3 nq 3 nq 2 note: pll_bypass, oe_ref, oe[3:0] and fsel[1:0] are interna lly pull ed down so no external comp onents are required to s elect the defaults. if external pull -up/down n eeded, see " logic control inp ut exampl es" s hown at le ft. c2 1p f c1 1pf xta l_ in x1 25mhz (12pf ) xta l_ out zo = 50 o hm r3 50 r4 50 zo = 50 o hm r2 50 3.3v pecl driv er c3 0. 1 u f 3. 3v c4 10uf fb1 bl m1 8b b2 21 sn 1 1 2 r1 5 c5 10uf c6 0. 1u f c7 0.1uf vd da place ea ch 0.1uf b ypass cap directly adjacent to its co rrespondi ng vdd or vdda pin. fsel0 fsel1 oe 0 oe 3 oe 2 oe 1 oe _r ef pll_bypass clk_sel r5 475 zo = 50 zo = 50 ref _ou t 1" to 14" 0" to 18" r6 33 0.5" to 3.5" r7 33 hcsl termination pci e xpress a dd-in ca rd o ptional pci express point-to-point connection r8 50 zo = 50 zo = 50 r9 50 r10 33 zo = 50 r11 50 zo = 50 r12 50 r13 33 hcsl_receiv er + - hcsl_receiv er + - c8 0. 1 u f c9 0.1uf c10 0.1uf c11 0.1uf vd d
idt8v41n004nlgi revision a december 18 , 2012 18 ?2012 integrated device technology, inc. IDT8V41N004I data sheet femtoclock ? ng crystal-to-hcsl clock generator pci express application note pci express jitter analysis methodology models the system response to reference clock jitter. the block diagram below shows the most frequently used common clock architecture in which a copy of the reference clock is provided to both ends of the pci express link. in the jitter analysis, the transmit (tx) and receive (rx) serdes plls are modeled as well as the phase in terpolator in the receiver. these transfer functions are called h1, h2, and h3 respectively. the overall system transfer function at the receiver is: the jitter spectrum seen by the receiv er is the result of applying this system transfer function to the clock spectrum x(s) and is: in order to generate time domain jitter numbers, an inverse fourier transform is performed on x(s)*h3(s) * [h1(s) - h2(s)]. pci express common clock architecture for pci express gen 1 , one transfer function is defined and the evaluation is performed over the ent ire spectrum: dc to nyquist (e.g for a 100mhz reference clock: 0hz ? 50mhz) and the jitter result is reported in peak-peak. pcie gen 1 magnitude of transfer function for pci express gen 2 , two transfer functions are defined with 2 evaluation ranges and the final jitter number is reported in rms. the two evaluation ranges for pci express gen 2 are 10khz ? 1.5mhz (low band) and 1.5mhz ? nyquist (high band). the plots show the individual transfer functions as well as the overall transfer function ht. pcie gen 2a magnitude of transfer function pcie gen 2b magnitude of transfer function for pci express gen 3 , one transfer function is defined and the evaluation is performed over the entire spectrum. the transfer function parameters are different from gen 1 and the jitter result is reported in rms. pcie gen 3 magnitude of transfer function for a more thorough overview of pci express jitter analysis methodology, please refer to idt application note pci express reference clock requirements. ht s ?? h3 s ?? h1 s ?? h2 s ?? ? ?? ? = ys ?? xs ?? h3 s ?? ? h1 s ?? h2 s ?? ? ?? ? =
idt8v41n004nlgi revision a december 18 , 2012 19 ?2012 integrated device technology, inc. IDT8V41N004I data sheet femtoclock ? ng crystal-to-hcsl clock generator vfqfn epad thermal release path in order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the printed circuit board (pcb) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in figure 5. the solderable area on the pcb, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. sufficient clearance should be designed on the pcb between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. while the land pattern on the pcb provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are nece ssary to effectively conduct from the surface of the pcb to the gro und plane(s). the land pattern must be connected to ground through thes e vias. the vias act as ?heat pipes?. the number of vias (i.e. ?h eat pipes?) are application specific and dependent upon the package power dissipation as well as electrical conductivity requiremen ts. thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. it is recommended to use as many vias connected to ground as possible. it is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. this is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal la nd. precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. note: these recommendations are to be used as a guideline only. for further information, please refer to the application note on the surface mount assembly of amkor?s thermally/ electrically enhance leadframe base package, amkor technology. figure 5. p.c. assembly for exposed pad thermal release path ? side view (drawing not to scale) solder solder pin pin exposed heat slug pin pad pin pad ground plane land pattern (ground pad) thermal via
idt8v41n004nlgi revision a december 18 , 2012 20 ?2012 integrated device technology, inc. IDT8V41N004I data sheet femtoclock ? ng crystal-to-hcsl clock generator recommended termination figure 6a is the recommended source termination for applications where the driver and receiver will be on a separate pcbs. this termination is the standard for pci express? and hcsl output types. all traces should be 50 ? impedance single-ended or 100 ? differential. figure 6a. recommended source termination (where the driver and receiver will be on separate pcbs) figure 6b is the recommended termination for applications where a point-to-point connection can be us ed. a point-to-point connection contains both the driver and the receiver on the same pcb. with a matched termination at the receiver, transmission-line reflections will be minimized. in addition, a series resistor (rs) at the driver offers flexibility and can help dampen unwanted reflections. the optional resistor can range from 0 ? to 33 ? . all traces should be 50 ? impedance single-ended or 100 ? differential. figure 6b. recommended termination (where a point-to-point connection can be used) 0-0.2" pci express l1 l1 1-14" driver rs 0.5" max l3 l4 l2 l2 49.9 +/- 5% 22 to 33 +/-5% rt l3 l4 l5 0.5 - 3.5" l5 connector pci express add-in card pci express 0-0.2" pci express 0-0.2" 0-18" l1 l1 rs driver 0.5" max l3 l3 l2 l2 49.9 +/- 5% 0 to 33 0 to 33 rt
idt8v41n004nlgi revision a december 18 , 2012 21 ?2012 integrated device technology, inc. IDT8V41N004I data sheet femtoclock ? ng crystal-to-hcsl clock generator power considerations this section provides information on power dissipati on and junction temperature for the IDT8V41N004I. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the IDT8V41N004I is the sum of the core power plus analog power plus the power dissipation at t he outputs. the following is the power dissipation for v dd = 3.3v + 5% = 3.465v, which gives worst case results. note: please refer to section 3 for details on calculating power dissipation at the outputs. ? power (core) max = v dd_max * (i dd_max + i dda_max ) = 3.465v * (121ma + 31ma) = 526.7mw ? power (outputs) max = 44.5mw/loaded output pair if all outputs are loaded, the total power is 5 * 44.5mw = 222.5mw total power_ max = (3.465v, if all outputs ar e loaded) = 526.7mw + 222.5mw = 749.2mw 2. junction temperature. junction temperature, tj, is the temperatur e at the junction of the bond wire and bo nd pad directly affects the reliability of the device. the maximum recommended junction temperature is 125c. limiting the in ternal transistor junction temperature, tj, to 125c ensures that the bond wire and bond pad temperature remains below 125c. the equation for tj is as follows: tj = ? ja * pd_total + t a tj = junction temperature ? ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ? ja must be used. assuming no air flow and a multi-layer board, the appropriate value is 33.1c/w per table 7 below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 0.749w * 33.1c/w = 109.8c. this is below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). table 7. thermal resistance ? ja for 32 lead vfqfn, forced convection ? ja vs. air flow meters per second 013 multi-layer pcb, jedec standard test boards 33.1c/w 28.1c/w 25.4c/w
idt8v41n004nlgi revision a december 18 , 2012 22 ?2012 integrated device technology, inc. IDT8V41N004I data sheet femtoclock ? ng crystal-to-hcsl clock generator 3. calculations and equations. the purpose of this section is to calculate power dissipation on the ic per hcsl output pairs. hcsl output driver circuit and termination are shown in figure 7. figure 7. hcsl driver circuit and termination hcsl is a current steering output which sour ces a maximum of 17ma of current per output. to calculate worst case on-chip power dissipation, use the following equations which assume a 50 ? load to ground. the highest power dissipation occurs at v dd _ max . power = (v dd_max ? v out ) * i out since v out = i out * r l power = (v dd_max ? i out * r l ) * i out = (3.465v ? 17ma * 50 ? ) * 17ma total power dissipation per output pair = 44.5mw v dd v out r l 50 ic ? i out = 17ma r ref = 475 1%
idt8v41n004nlgi revision a december 18 , 2012 23 ?2012 integrated device technology, inc. IDT8V41N004I data sheet femtoclock ? ng crystal-to-hcsl clock generator reliability information table 7. ? ja vs. air flow table for a 32 lead vfqfn transistor count the transistor count for IDT8V41N004I is: 24,809 ? ja vs. air flow meters per second 013 multi-layer pcb, jedec standard te st boards 33.1c/w 28.1c/w 25.4c/w
idt8v41n004nlgi revision a december 18 , 2012 24 ?2012 integrated device technology, inc. IDT8V41N004I data sheet femtoclock ? ng crystal-to-hcsl clock generator 32 lead vfqfn package out line and package dimensions
idt8v41n004nlgi revision a december 18 , 2012 25 ?2012 integrated device technology, inc. IDT8V41N004I data sheet femtoclock ? ng crystal-to-hcsl clock generator ordering information table 8. ordering information part/order number marking package shipping packaging temperature 8v41n004nlgi idt8v41n004nlgi ?lead-free? 32 lead vfqfn tray -40 ? c to 85 ? c 8v41n004nlgi8 idt8v41n004nlgi ?lead-free? 32 lead vfqfn tape & reel -40 ? c to 85 ? c
IDT8V41N004I data sheet femtoclock ? ng crystal-to-hcsl clock generator disclaimer integrated device technology, inc. (idt) and its subsid iaries reserve the right to modify the products and/or specif ications described herein at any time and at idt?s sole discre tion. all information in this document, including descriptions of product features a nd performance, is subject to change wit hout notice. performance specifications and the operating parameters of the de scribed products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. the information containe d herein is provided without re presentation or warranty of a ny kind, whether express or implie d, including, but not limited to, the suitability of idt?s products for any par ticular purpose, an implied warranty of merchantability, or non-infringement of the in tellectual property rights of others. this document is presented only as a guide and does not convey any license under intellectual property rights of idt or any third parties. idt?s products are not intended for use in applications involving extreme environmental conditions or in life support systems o r similar devices where the failure or malfunction of an idt product can be reasonably expected to signifi- cantly affect the health or safety of users. anyone using an id t product in such a manner does so at their own risk, absent an express, written agreement by idt. integrated device technology, idt and the id t logo are registered trademarks of idt. other trademarks and service marks used he rein, including protected names, logos and designs, ar e the property of idt or their respective third party owners. copyright 2012. all rights reserved. 6024 silver creek valley road san jose, california 95138 sales 800-345-7015 (inside usa) +408-284-8200 (outside usa) fax: 408-284-2775 www.idt.com/go/contactidt technical support netcom@idt.com +480-763-2056 we?ve got your timing solution

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